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| author | Salvatore Bonaccorso <carnil@debian.org> | 2021-02-28 21:14:58 +0100 |
|---|---|---|
| committer | Salvatore Bonaccorso <carnil@debian.org> | 2021-02-28 21:15:50 +0100 |
| commit | 16354f3f4a779d3ac201e35f818a5aef6ae7d440 (patch) | |
| tree | 06f4f84a9e8934c69c91330c4965672fd02bf64d | |
| parent | 908e080fcc6d00679cced1b92026759385164ad3 (diff) | |
| download | linux-debian-16354f3f4a779d3ac201e35f818a5aef6ae7d440.tar.gz | |
[x86] drm/i915/gt: Correct surface base address for renderclear
| -rw-r--r-- | debian/changelog | 1 | ||||
| -rw-r--r-- | debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch | 37 | ||||
| -rw-r--r-- | debian/patches/series | 1 |
3 files changed, 39 insertions, 0 deletions
diff --git a/debian/changelog b/debian/changelog index c0fa4a5e3..1248b9b1d 100644 --- a/debian/changelog +++ b/debian/changelog @@ -351,6 +351,7 @@ linux (5.10.19-1) UNRELEASED; urgency=medium (CVE-2020-25639) * [x86] drm/i915/gt: One more flush for Baytrail clear residuals * [x86] drm/i915/gt: Flush before changing register state + * [x86] drm/i915/gt: Correct surface base address for renderclear [ Vincent Blut ] * [x86] Enable PWM_CRC (Closes: #982808) diff --git a/debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch b/debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch new file mode 100644 index 000000000..dcaa72e13 --- /dev/null +++ b/debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch @@ -0,0 +1,37 @@ +From: Chris Wilson <chris@chris-wilson.co.uk> +Date: Wed, 10 Feb 2021 12:27:28 +0000 +Subject: drm/i915/gt: Correct surface base address for renderclear +Origin: https://cgit.freedesktop.org/drm-intel/commit/?id=1914911f4aa08ddc05bae71d3516419463e0c567 + +The surface_state_base is an offset into the batch, so we need to pass +the correct batch address for STATE_BASE_ADDRESS. + +Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") +Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> +Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> +Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> +Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> +Cc: Hans de Goede <hdegoede@redhat.com> +Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> +Cc: <stable@vger.kernel.org> # v5.7+ +Link: https://patchwork.freedesktop.org/patch/msgid/20210210122728.20097-1-chris@chris-wilson.co.uk +--- + drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c +index e403eb046a43..de575fdb033f 100644 +--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c ++++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c +@@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch, + /* general */ + *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; + /* surface */ +- *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY; ++ *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY; + /* dynamic */ + *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; + /* indirect */ +-- +2.30.1 + diff --git a/debian/patches/series b/debian/patches/series index 9dc573ee1..9395b1e19 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -78,6 +78,7 @@ bugfix/x86/x86-32-disable-3dnow-in-generic-config.patch bugfix/mips/mips-support-binutils-configured-with-enable-mips-fi.patch bugfix/x86/drm-i915-gt-One-more-flush-for-Baytrail-clear-residu.patch bugfix/x86/drm-i915-gt-Flush-before-changing-register-state.patch +bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch # Arch features features/arm64/arm64-dts-rockchip-Add-basic-support-for-Kobol-s-Hel.patch |