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authorSalvatore Bonaccorso <carnil@debian.org>2021-03-01 20:47:11 +0100
committerSalvatore Bonaccorso <carnil@debian.org>2021-03-01 20:47:11 +0100
commit45c684f82d492f626d920144c49300214186f95a (patch)
tree93612dac0239ade6d971664be24cb1291dad3532
parent16354f3f4a779d3ac201e35f818a5aef6ae7d440 (diff)
downloadlinux-debian-45c684f82d492f626d920144c49300214186f95a.tar.gz
[x86] i915 fixes: replace header with upstream'ed commits
Gbp-Dch: Ignore
-rw-r--r--debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch4
-rw-r--r--debian/patches/bugfix/x86/drm-i915-gt-Flush-before-changing-register-state.patch4
2 files changed, 6 insertions, 2 deletions
diff --git a/debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch b/debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch
index dcaa72e13..8523c4a02 100644
--- a/debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch
+++ b/debian/patches/bugfix/x86/drm-i915-gt-Correct-surface-base-address-for-renderc.patch
@@ -1,7 +1,7 @@
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed, 10 Feb 2021 12:27:28 +0000
Subject: drm/i915/gt: Correct surface base address for renderclear
-Origin: https://cgit.freedesktop.org/drm-intel/commit/?id=1914911f4aa08ddc05bae71d3516419463e0c567
+Origin: https://git.kernel.org/linus/81ce8f04aa96f7f6cae05770f68b5d15be91f5a2
The surface_state_base is an offset into the batch, so we need to pass
the correct batch address for STATE_BASE_ADDRESS.
@@ -15,6 +15,8 @@ Cc: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: <stable@vger.kernel.org> # v5.7+
Link: https://patchwork.freedesktop.org/patch/msgid/20210210122728.20097-1-chris@chris-wilson.co.uk
+(cherry picked from commit 1914911f4aa08ddc05bae71d3516419463e0c567)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/debian/patches/bugfix/x86/drm-i915-gt-Flush-before-changing-register-state.patch b/debian/patches/bugfix/x86/drm-i915-gt-Flush-before-changing-register-state.patch
index 9cf347227..5253c97a9 100644
--- a/debian/patches/bugfix/x86/drm-i915-gt-Flush-before-changing-register-state.patch
+++ b/debian/patches/bugfix/x86/drm-i915-gt-Flush-before-changing-register-state.patch
@@ -1,7 +1,7 @@
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon, 25 Jan 2021 22:02:47 +0000
Subject: drm/i915/gt: Flush before changing register state
-Origin: https://cgit.freedesktop.org/drm-intel/commit/?id=d30bbd62b1bfd9e0a33c3583c5a9e5d66f60cbd7
+Origin: https://git.kernel.org/linus/d5109f739c9f14a3bda249cb48b16de1065932f0
Flush; invalidate; change registers; invalidate; flush.
@@ -17,6 +17,8 @@ Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125220247.31701-1-chris@chris-wilson.co.uk
+(cherry picked from commit d30bbd62b1bfd9e0a33c3583c5a9e5d66f60cbd7)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 1 +
1 file changed, 1 insertion(+)