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| author | Andy Polyakov <appro@openssl.org> | 2011-05-27 15:32:43 +0000 |
|---|---|---|
| committer | Andy Polyakov <appro@openssl.org> | 2011-05-27 15:32:43 +0000 |
| commit | 4bb90087d745c26401e09a3bd10137d7b05e9ea3 (patch) | |
| tree | 39f872716920503d9d88b0fb0436e05042b5dd84 /crypto/x86_64cpuid.pl | |
| parent | 6715034002f2d7831b234c50a2a072320905cafe (diff) | |
| download | openssl-4bb90087d745c26401e09a3bd10137d7b05e9ea3.tar.gz | |
x86[_64]cpuid.pl: harmonize usage of reserved bits #20 and #30.
Diffstat (limited to 'crypto/x86_64cpuid.pl')
| -rw-r--r-- | crypto/x86_64cpuid.pl | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/crypto/x86_64cpuid.pl b/crypto/x86_64cpuid.pl index 84b1cbe85f..7b76522bd8 100644 --- a/crypto/x86_64cpuid.pl +++ b/crypto/x86_64cpuid.pl @@ -124,13 +124,14 @@ OPENSSL_ia32_cpuid: .Lnocacheinfo: mov \$1,%eax cpuid + and \$0xbfefffff,%edx # force reserved bits to 0 cmp \$0,%r9d jne .Lnotintel - or \$0x00100000,%edx # use reserved 20th bit to engage RC4_CHAR + or \$0x40000000,%edx # set reserved bit#30 on Intel CPUs and \$15,%ah cmp \$15,%ah # examine Family ID - je .Lnotintel - or \$0x40000000,%edx # use reserved bit to skip unrolled loop + jne .Lnotintel + or \$0x00100000,%edx # set reserved bit#20 to engage RC4_CHAR .Lnotintel: bt \$28,%edx # test hyper-threading bit jnc .Lgeneric |