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| author | Andy Polyakov <appro@openssl.org> | 2011-05-27 15:32:43 +0000 |
|---|---|---|
| committer | Andy Polyakov <appro@openssl.org> | 2011-05-27 15:32:43 +0000 |
| commit | 4bb90087d745c26401e09a3bd10137d7b05e9ea3 (patch) | |
| tree | 39f872716920503d9d88b0fb0436e05042b5dd84 /doc | |
| parent | 6715034002f2d7831b234c50a2a072320905cafe (diff) | |
| download | openssl-4bb90087d745c26401e09a3bd10137d7b05e9ea3.tar.gz | |
x86[_64]cpuid.pl: harmonize usage of reserved bits #20 and #30.
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/crypto/OPENSSL_ia32cap.pod | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/doc/crypto/OPENSSL_ia32cap.pod b/doc/crypto/OPENSSL_ia32cap.pod index af6b4f3a4d..3f6458c6bd 100644 --- a/doc/crypto/OPENSSL_ia32cap.pod +++ b/doc/crypto/OPENSSL_ia32cap.pod @@ -37,14 +37,13 @@ moment of this writing following bits are significant: =item bit #28 denoting Hyperthreading, which is used to distiguish cores with shared cache; -=item bit #30, reserved by Intel, is used to choose among RC4 code - paths; +=item bit #30, reserved by Intel, denotes specifically Intel CPUs; =item bit #33 denoting availability of PCLMULQDQ instruction; =item bit #41 denoting SSSE3, Supplemental SSE3, support; -=item bit #43 denoting AMD XOP support (forced to zero on Intel); +=item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs); =item bit #57 denoting AES-NI instruction set extension; |