From 926bfc3bc0cfea976533c8eba8cda1fa298124e2 Mon Sep 17 00:00:00 2001
From: Takashi Kokubun <takashikkbn@gmail.com>
Date: Wed, 22 Nov 2023 15:13:32 -0800
Subject: YJIT: Avoid a register spill on arm64 (#9014)

---
 bootstraptest/test_yjit.rb | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'bootstraptest')

diff --git a/bootstraptest/test_yjit.rb b/bootstraptest/test_yjit.rb
index a7ef90ba74..f55c319707 100644
--- a/bootstraptest/test_yjit.rb
+++ b/bootstraptest/test_yjit.rb
@@ -4244,3 +4244,10 @@ assert_equal 'true', %q{
   def entry = yield
   entry { true }
 }
+
+assert_normal_exit %q{
+  ivars = 1024.times.map { |i| "@iv_#{i} = #{i}\n" }.join
+  Foo = Class.new
+  Foo.class_eval "def initialize() #{ivars} end"
+  Foo.new
+}
-- 
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