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| author | Alex Sierra <alex.sierra@amd.com> | 2021-01-15 17:03:18 -0600 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-04-20 21:48:58 -0400 |
| commit | 9dd9cc2f7433cdf389049c91c87c09eaccece373 (patch) | |
| tree | 95d0b32675146d4edd48ea6f0bc4219cda3434e8 | |
| parent | 90d7d3eda5796fa48048f1114b0aa090c5465d17 (diff) | |
| download | linux-9dd9cc2f7433cdf389049c91c87c09eaccece373.tar.gz | |
drm/amdgpu: enable 48-bit IH timestamp counter
By default this timestamp is 32 bit counter. It gets
overflowed in around 10 minutes.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index ca8efa5c6978..2f17c8a57015 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -104,6 +104,7 @@ static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, tmp = RREG32(ih_regs->ih_rb_cntl); tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); /* enable_intr field is only valid in ring0 */ if (ih == &adev->irq.ih) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); |