diff options
| author | Andy Polyakov <appro@openssl.org> | 2011-05-27 15:32:43 +0000 |
|---|---|---|
| committer | Andy Polyakov <appro@openssl.org> | 2011-05-27 15:32:43 +0000 |
| commit | 4bb90087d745c26401e09a3bd10137d7b05e9ea3 (patch) | |
| tree | 39f872716920503d9d88b0fb0436e05042b5dd84 /crypto/x86cpuid.pl | |
| parent | 6715034002f2d7831b234c50a2a072320905cafe (diff) | |
| download | openssl-4bb90087d745c26401e09a3bd10137d7b05e9ea3.tar.gz | |
x86[_64]cpuid.pl: harmonize usage of reserved bits #20 and #30.
Diffstat (limited to 'crypto/x86cpuid.pl')
| -rw-r--r-- | crypto/x86cpuid.pl | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/crypto/x86cpuid.pl b/crypto/x86cpuid.pl index f424c2debe..716f44da92 100644 --- a/crypto/x86cpuid.pl +++ b/crypto/x86cpuid.pl @@ -92,13 +92,15 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); } &set_label("nocacheinfo"); &mov ("eax",1); &cpuid (); + &and ("edx",~(1<<20|1<<30)); # force reserved bits to 0 &cmp ("ebp",0); - &jne (&label("notP4")); + &jne (&label("notintel")); + &or ("edx",1<<30); # set reserved bit#30 on Intel CPUs &and (&HB("eax"),15); # familiy ID &cmp (&HB("eax"),15); # P4? - &jne (&label("notP4")); - &or ("edx",1<<20); # use reserved bit to engage RC4_CHAR -&set_label("notP4"); + &jne (&label("notintel")); + &or ("edx",1<<20); # set reserved bit#20 to engage RC4_CHAR +&set_label("notintel"); &bt ("edx",28); # test hyper-threading bit &jnc (&label("generic")); &and ("edx",0xefffffff); |