Port print_str to new backend (https://github.com/Shopify/ruby/pull/318)

* ADR and ADRP for AArch64

* Implement Op::Jbe on X86

* Lera instruction

* Op::BakeString

* LeaPC -> LeaLabel

* Port print_str to the new backend

* Port print_value to the new backend

* Port print_ptr to the new backend

* Write null-terminators in Op::BakeString

* Fix up rebase issues on print-str port

* Add back in panic for X86 backend for unsupported instructions being lowered

* Fix target architecture

3 files changed, 151 insertions, 0 deletions

diff --git a/yjit/src/asm/arm64/inst/mod.rs b/yjit/src/asm/arm64/inst/mod.rs
index 9dfc923f53..752ee64aa3 100644
--- a/yjit/src/asm/arm64/inst/mod.rs
+++ b/yjit/src/asm/arm64/inst/mod.rs
@@ -14,6 +14,7 @@ mod logical_imm;
 mod logical_reg;
 mod mov;
 mod nop;
+mod pc_rel;
 mod shift_imm;
 mod store;
 mod sys_reg;
@@ -31,6 +32,7 @@ pub use logical_imm::LogicalImm;
 pub use logical_reg::LogicalReg;
 pub use mov::Mov;
 pub use nop::Nop;
+pub use pc_rel::PCRelative;
 pub use shift_imm::ShiftImm;
 pub use store::Store;
 pub use sys_reg::SysReg;
diff --git a/yjit/src/asm/arm64/inst/pc_rel.rs b/yjit/src/asm/arm64/inst/pc_rel.rs
new file mode 100644
index 0000000000..fa330cb9d6
--- /dev/null
+++ b/yjit/src/asm/arm64/inst/pc_rel.rs
@@ -0,0 +1,107 @@
+/// Which operation to perform for the PC-relative instruction.
+enum Op {
+    /// Form a PC-relative address.
+    ADR = 0,
+
+    /// Form a PC-relative address to a 4KB page.
+    ADRP = 1
+}
+
+/// The struct that represents an A64 PC-relative address instruction that can
+/// be encoded.
+///
+/// ADR
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
+/// |           1    0  0  0  0                                                                                     |
+/// | op immlo                    immhi........................................................... rd.............. |
+/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+///
+pub struct PCRelative {
+    /// The number for the general-purpose register to load the address into.
+    rd: u8,
+
+    /// The number of bytes to add to the PC to form the address.
+    imm: i32,
+
+    /// Which operation to perform for this instruction.
+    op: Op
+}
+
+impl PCRelative {
+    /// ADR
+    /// https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/ADR--Form-PC-relative-address-
+    pub fn adr(rd: u8, imm: i32) -> Self {
+        Self { rd, imm, op: Op::ADR }
+    }
+
+    /// ADRP
+    /// https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/ADRP--Form-PC-relative-address-to-4KB-page-
+    pub fn adrp(rd: u8, imm: i32) -> Self {
+        Self { rd, imm: imm >> 12, op: Op::ADRP }
+    }
+}
+
+/// https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Data-Processing----Immediate?lang=en
+const FAMILY: u32 = 0b1000;
+
+impl From<PCRelative> for u32 {
+    /// Convert an instruction into a 32-bit value.
+    fn from(inst: PCRelative) -> Self {
+        let immlo = (inst.imm & 0b11) as u32;
+        let mut immhi = ((inst.imm >> 2) & ((1 << 18) - 1)) as u32;
+
+        // Toggle the sign bit if necessary.
+        if inst.imm < 0 {
+            immhi |= (1 << 18);
+        }
+
+        0
+        | ((inst.op as u32) << 31)
+        | (immlo << 29)
+        | (FAMILY << 25)
+        | (immhi << 5)
+        | inst.rd as u32
+    }
+}
+
+impl From<PCRelative> for [u8; 4] {
+    /// Convert an instruction into a 4 byte array.
+    fn from(inst: PCRelative) -> [u8; 4] {
+        let result: u32 = inst.into();
+        result.to_le_bytes()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_adr_positive() {
+        let inst = PCRelative::adr(0, 5);
+        let result: u32 = inst.into();
+        assert_eq!(0x30000020, result);
+    }
+
+    #[test]
+    fn test_adr_negative() {
+        let inst = PCRelative::adr(0, -5);
+        let result: u32 = inst.into();
+        assert_eq!(0x70ffffc0, result);
+    }
+
+    #[test]
+    fn test_adrp_positive() {
+        let inst = PCRelative::adrp(0, 0x4000);
+        let result: u32 = inst.into();
+        assert_eq!(0x90000020, result);
+    }
+
+    #[test]
+    fn test_adrp_negative() {
+        let inst = PCRelative::adrp(0, -0x4000);
+        let result: u32 = inst.into();
+        assert_eq!(0x90ffffe0, result);
+    }
+}
diff --git a/yjit/src/asm/arm64/mod.rs b/yjit/src/asm/arm64/mod.rs
index 7adc1a2745..ca69b33d9e 100644
--- a/yjit/src/asm/arm64/mod.rs
+++ b/yjit/src/asm/arm64/mod.rs
@@ -94,6 +94,38 @@ pub fn adds(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
     cb.write_bytes(&bytes);
 }
 
+/// ADR - form a PC-relative address and load it into a register
+pub fn adr(cb: &mut CodeBlock, rd: A64Opnd, imm: A64Opnd) {
+    let bytes: [u8; 4] = match (rd, imm) {
+        (A64Opnd::Reg(rd), A64Opnd::Imm(imm)) => {
+            assert!(rd.num_bits == 64, "The destination register must be 64 bits.");
+            assert!(imm_fits_bits(imm, 21), "The immediate operand must be 21 bits or less.");
+
+            PCRelative::adr(rd.reg_no, imm as i32).into()
+        },
+        _ => panic!("Invalid operand combination to adr instruction."),
+    };
+
+    cb.write_bytes(&bytes);
+}
+
+/// ADRP - form a PC-relative address to a 4KB page and load it into a register.
+/// This is effectively the same as ADR except that the immediate must be a
+/// multiple of 4KB.
+pub fn adrp(cb: &mut CodeBlock, rd: A64Opnd, imm: A64Opnd) {
+    let bytes: [u8; 4] = match (rd, imm) {
+        (A64Opnd::Reg(rd), A64Opnd::Imm(imm)) => {
+            assert!(rd.num_bits == 64, "The destination register must be 64 bits.");
+            assert!(imm_fits_bits(imm, 32), "The immediate operand must be 32 bits or less.");
+
+            PCRelative::adrp(rd.reg_no, imm as i32).into()
+        },
+        _ => panic!("Invalid operand combination to adr instruction."),
+    };
+
+    cb.write_bytes(&bytes);
+}
+
 /// AND - and rn and rm, put the result in rd, don't update flags
 pub fn and(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
     let bytes: [u8; 4] = match (rd, rn, rm) {
@@ -629,6 +661,16 @@ mod tests {
     }
 
     #[test]
+    fn test_adr() {
+        check_bytes("aa000010", |cb| adr(cb, X10, A64Opnd::new_imm(20)));
+    }
+
+    #[test]
+    fn test_adrp() {
+        check_bytes("4a000090", |cb| adrp(cb, X10, A64Opnd::new_imm(0x8000)));
+    }
+
+    #[test]
     fn test_and_register() {
         check_bytes("2000028a", |cb| and(cb, X0, X1, X2));
     }