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author | Takashi Kokubun <takashikkbn@gmail.com> | 2022-12-01 16:13:38 -0800 |
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committer | GitHub <noreply@github.com> | 2022-12-01 16:13:38 -0800 |
commit | dcbea7671be74a328f115c6410980f54c872c478 (patch) | |
tree | 9ee1ce4473273d521fb8871d30fab83fd8b6b612 /yjit/src/asm | |
parent | 8ffa8fc192f4c4005fd2216108ee82876b4165cb (diff) | |
download | ruby-dcbea7671be74a328f115c6410980f54c872c478.tar.gz |
YJIT: Respect destination num_bits on STUR (#6848)
Diffstat (limited to 'yjit/src/asm')
-rw-r--r-- | yjit/src/asm/arm64/mod.rs | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/yjit/src/asm/arm64/mod.rs b/yjit/src/asm/arm64/mod.rs index 04660e580e..9bc697ecfb 100644 --- a/yjit/src/asm/arm64/mod.rs +++ b/yjit/src/asm/arm64/mod.rs @@ -906,7 +906,7 @@ pub fn stur(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) { assert!(rn.num_bits == 32 || rn.num_bits == 64); assert!(mem_disp_fits_bits(rn.disp), "Expected displacement to be 9 bits or less"); - LoadStore::stur(rt.reg_no, rn.base_reg_no, rn.disp as i16, rt.num_bits).into() + LoadStore::stur(rt.reg_no, rn.base_reg_no, rn.disp as i16, rn.num_bits).into() }, _ => panic!("Invalid operand combination to stur instruction.") }; @@ -1499,11 +1499,16 @@ mod tests { } #[test] - fn test_stur() { + fn test_stur_64_bits() { check_bytes("6a0108f8", |cb| stur(cb, X10, A64Opnd::new_mem(64, X11, 128))); } #[test] + fn test_stur_32_bits() { + check_bytes("6a0108b8", |cb| stur(cb, X10, A64Opnd::new_mem(32, X11, 128))); + } + + #[test] fn test_sub_reg() { check_bytes("200002cb", |cb| sub(cb, X0, X1, X2)); } |